The present invention relates in general to a method of fabrication of a semiconductor integrated circuit device, and more particularly, the invention relates to a technology which may be effectively applied to an inspection process for inspecting an integrated circuit formed on a semiconductor wafer by utilizing a semiconductor inspection apparatus including a probe card.
A technology (refer to the Patent Document 1), has been proposed for providing, for example, a probe card, which is formed of a multilayer wiring board, in which high-speed operation signals and minute signals can be measured accurately without any influence from noise. This is achieved by arranging a connecting means to be connected to a tester head in a connecting region of the external circumferential portion to make it possible to form, in the component mounting region in the internal circumferential portion, an electronic circuit for measuring the characteristic of a semiconductor device formed within a semiconductor wafer, which serves as the inspection object, by providing a shield pattern in a signal pattern for electrically connecting to the probe from the connecting region so as to surround this signal pattern, by providing a shield member to the connecting pins inserted to the connecting means, and by connecting such shield member to the shield pattern.
[Patent Document 1]                Japanese Unexamined Patent Publication No. Hei 11(1999)-44709        